Register D | Research date: 2026-04-26 | Mode: New position / research > Industry primer: Semiconductor Burn-In & SLT covered in industry-log 2026-04-26
Register D | Research date: 2026-04-26 | Mode: New position / research Industry primer: Semiconductor Burn-In & SLT covered in industry-log 2026-04-26
Thesis (Bull): AEM is the world’s leading burn-in and system-level test (SLT) handler maker for advanced logic chips. After a brutal two-year Intel downcycle that collapsed revenue 56% from peak, the company is entering a structural inflection: a new unnamed AI/HPC anchor customer (widely speculated AMD or NVIDIA) is expected to overtake Intel as the largest customer by end-2026, while Intel’s own 18A ramp drives simultaneous equipment refresh at AEM’s legacy installed base. AEM’s PiXL thermal technology — capable of handling >2,000W per package under test — is non-replicable by standard handlers and positions the company as the only credible incumbent for the next generation of high-power AI chip validation. At S$399M revenue, the company is still well below its S$870M FY2022 peak; if the new customer ramp and Intel 18A thesis both deliver, a return toward S$700-800M revenue in the FY2027-28 timeframe appears plausible.
The problem: The stock has already run +90% YTD in 2026 to S$6.06. At 113x TTM P/E and 49x forward P/E, substantially all of the near-term ramp is now in the price. The risk/reward is less clear after a doubling. The new customer’s identity is unconfirmed, their order schedule is unknown, and Intel’s execution history warrants caution. Memory test (FY2026-27) adds option value but is unproven.
Price / market cap / EV: S$6.06 / S$1.91B / ~S$1.85B (net cash S$61M) Conviction level: Medium — thesis is real, but entry point is the question Target price: Not provided (buy/sell opinion reserved for pre-buy checklist skill) 52-week range: S$1.15 – S$6.15
AEM Holdings Ltd. (SGX: AWX) is a Singapore-listed semiconductor test equipment company specializing in burn-in and system-level test (SLT) solutions. In plain language: before a chip ships from the factory, it must be validated under real-world stress conditions — high temperature, real voltage, real workloads. AEM builds the hardware that does this at production scale. Its primary customer for 15+ years has been Intel; a new AI/HPC customer is now becoming its second major anchor.
Business model: Capital equipment (burn-in handlers, SLT cells, thermal systems) sold to chip manufacturers. Revenue is predominantly one-time on equipment; consumables (test contactors, sockets) and service contracts create modest recurring revenue tail. Gross margins ~25-27% — below ATE pure-plays (Teradyne/Advantest at 50%+) because AEM is a handler/integrator, not a tester OEM.
Geographic operations: Singapore (HQ + manufacturing), Malaysia (Penang — volume mfg), Vietnam (HCMC — assembly), Indonesia (Batam — assembly), Finland (Lieto — R&D + wafer/quantum probe). Sales presence in US, Ireland, Germany, Korea, China, France, Costa Rica, UK.
Segment revenue (FY2024, approx):
| Segment | Description | ~FY2024 Share |
|---|---|---|
| Test Cell Solutions (TCS) | Burn-in/SLT handlers, complete test cells, thermal systems | ~60-65% |
| Contract Manufacturing (CM) | EMS for third parties | ~20-25% |
| Instrumentation (INS) | Wafer-level test, cryogenic quantum probers | ~10-15% |
| Other | Engineering services, rapid prototyping | ~5% |
Every semiconductor chip — no matter how perfectly designed — contains manufacturing defects. Some defects are latent: the chip passes electrical tests at room temperature, normal voltage, and with simple test vectors, but fails in the field after hours or weeks of operation. These early-life failures (also called “infant mortality failures”) follow the Bathtub Curve: failure rate is high initially, drops as weak devices are eliminated, then rises again as devices age. The goal of burn-in and SLT is to catch the infant mortality failures at the factory, not in the customer’s data center.
Before AEM’s type of solution existed, chip makers relied on “soak” burn-in: large ovens that applied elevated temperature and voltage to packaged chips for 48-168 hours. This was slow, used enormous floor space, and gave no feedback during the stress period. As chips grew more complex, oven burn-in missed more failure modes.
Infant Mortality Failure Physics: Defects in semiconductor devices accelerate under elevated temperature and voltage stress. The Arrhenius equation describes this acceleration:
Acceleration Factor = exp[(Ea/k) × (1/T_use - 1/T_stress)]Where Ea is the activation energy of the failure
mechanism (~0.7 eV for oxide defects), k is Boltzmann’s
constant, T is temperature in Kelvin. At 125°C junction
temperature vs. 50°C operating temperature, this gives an acceleration
factor of ~5-10x — meaning a 24-hour burn-in screen is equivalent to
120-240 hours of field operation for early-life failures.
Why Thermal Control Is Critical: Modern AI chips (e.g., Intel’s Xeon Scalable or AMD’s EPYC, and to a greater extent NVIDIA’s B200 GPUs) dissipate enormous power: 400W-1,000W per package in production, with test conditions requiring even higher thermal loading. A handler must: 1. Apply precisely controlled elevated temperature to each device (not too hot — device damage; not too cool — insufficient screen) 2. Handle per-device variation in power dissipation in a parallel test cell (100+ devices tested simultaneously) 3. Remove heat at a rate matching device power dissipation, which is dynamic (changes with workload) 4. Maintain temperature stability across the full duration of the burn-in period
Standard handlers use forced-air convection — fine for low-power chips. AEM’s PiXL ATC uses direct liquid cooling with closed-loop thermal feedback, enabling per-device thermal control at power densities that air cooling cannot handle.
Key terminology: - Burn-in: Stress test under elevated temperature and voltage to accelerate and screen early-life failures - SLT (System-Level Test): Running the actual chip using real firmware, software, and realistic workloads; catches integration failures that ATE test vectors miss - ATE (Automatic Test Equipment): Traditional test equipment (Teradyne, Advantest) that applies structured electrical test vectors; good for structural and functional test, but test vectors can’t replicate all real-world failure modes - Handler: The mechanical system that picks, places, contacts, thermally controls, and recovers chips during test; AEM’s core product - DUT (Device Under Test): The chip being tested - HTOL (High-Temperature Operating Life): Extended burn-in qualification test (1,000+ hours) at maximum rated temperature; done on qualification lots, not production volumes - KGD (Known Good Die): Die verified as functional before advanced packaging; critical for chiplet architectures to avoid packaging cost on bad dies
[Package Chips] → [Load into Handler] → [Thermal Pre-conditioning]
→ [Electrical Contact Engagement] → [Apply Stress (Temp + Voltage)]
→ [Apply Workload (burn-in vectors or real firmware for SLT)]
→ [Monitor Response in Real-Time] → [Unload and Sort (Pass/Fail)]
→ [Final Test (ATE)] → [Ship to Customer]Step 1 — Load: Robots pick packaged chips from trays and place them into test sockets. Each socket makes electrical contact with the chip’s package pins or balls. At AEM’s parallelism levels, 100+ chips may be in contact simultaneously across an array of sockets.
Step 2 — Thermal engagement: PiXL ATC applies the prescribed temperature profile. The system circulates coolant (temperature-controlled fluid) through contact with each device or through a proximity thermal element, simultaneously measuring junction temperature via electrical signatures (ΔVBE method or equivalent). Feedback loop maintains target junction temperature ±1°C across all DUTs despite varying device power.
Step 3 — Stress application: Voltage is ramped to stress conditions (e.g., 10-15% above nominal Vdd). Test vectors (burn-in) or real workloads (SLT) are applied through the tester connected to the handler.
Step 4 — Monitoring: During stress, the system monitors for marginal behavior: slow response, intermittent bit errors, thermal events. SLT platforms log actual performance data, enabling statistical screening (not just pass/fail).
Step 5 — Unload and sort: After stress cycle, chips are returned to room temperature. Electrical re-test identifies failures that occurred during stress. Fail chips are sorted out.
Hardest engineering challenge: Thermal uniformity at scale. Each chip’s power dissipation varies with workload and silicon characteristics. At 100+ sites per cell, delivering independent thermal control without cross-heating between adjacent DUTs, while maintaining mechanical reliability of the contact interface over millions of cycles, is the defining challenge.
| Metric | Why It Matters | AEM Current |
|---|---|---|
| Max power per DUT | Defines which chips AEM can test | >2,000W |
| Max package size | Physical limit of handler contact area | >200mm x 200mm |
| Sites per cell | Higher = more chips per test hour = lower cost of test | 100s of sites |
| Thermal uniformity (ΔT) | ±1-2°C target; worse = higher yield loss or missed screens | Industry-leading (patented) |
| Contact resistance stability | Determines how many contact cycles before socket replacement | Thousands of cycles |
| Throughput (chips/hour) | Cost of test is inversely proportional | Not publicly disclosed |
Investor-trackable leading indicators: - Intel manufacturing utilization and back-end test capex commentary - New AI chip power density trends (higher power = greater need for AEM-class thermal solutions) - AEM SLT site count announcements (40,000+ at Intel = high installed base lock-in)
AMPS Platform (Asynchronous Modular Parallel and Smart): AEM’s flagship system is the AMPS — an asynchronous, modular, highly parallel test cell. Each AMPS cell runs independently (asynchronous = no master clock coordinating all cells), so a failure in one cell doesn’t halt others. Cells can be configured for SLT, final test, or burn-in, all in one physical unit. The HDMT (High Density Modular Test) handler, developed in co-development with Intel from 2015, is AEM’s highest-volume product for Intel’s back-end test operations. AMPS-BI is the burn-in extension launched for AI/HPC chips.
PiXL Active Thermal Control (ATC): AEM’s patented thermal system. Works across all AMPS test insertions: engineering labs through high-volume manufacturing. PiXL is the differentiating technology enabling >2,000W per device handling at package sizes >200mm x 200mm. Integrates eco-friendly coolants. The system actively monitors and adjusts per-DUT thermal conditions in real time, providing better yield and faster time-to-market by reducing thermal-induced test escapes.
ASP: Not publicly disclosed. Capital equipment pricing in this space typically runs $500K-$5M per system depending on configuration and parallelism. AEM’s per-unit ASP is lower than Teradyne/Advantest (which are full ATE solutions) but systems are deployed in very large quantities at Intel.
Consumables tail: Test sockets (contactors) and thermal interface materials require periodic replacement — measured in millions of cycles before wear. This creates a recurring revenue stream, though AEM doesn’t separately break out consumables revenue.
Wafer-level test (Finland): AEM’s Finnish operations (formerly Afore — acquired) specialize in wafer-level testing. The team in Lieto, Finland leads AEM’s specialty wafer probe segment, serving compound semiconductor and power device markets.
Cryogenic wafer probers (quantum computing): In partnership with Bluefors (Finland — private, industry leader in Dilution Refrigerators), AEM developed wafer probers capable of testing quantum chips at sub-2 Kelvin temperatures (colder than outer space). This enabled testing of quantum computing wafers without removing them from the cryogenic environment. Commercial volumes are small; Quantum is a nascent market. Patent portfolio developed with Bluefors. AEM delivered “multiple 300mm cryogenic wafer probers” to quantum customers in 2024.
Why it matters to thesis: Small today, but positions AEM ahead in quantum test — a market where first-mover matters enormously (chip qualification requires specific test infrastructure, creating lock-in).
AEM provides EMS (electronics manufacturing services) for third-party customers, leveraging its manufacturing capacity in Singapore and Southeast Asia. This segment provides revenue floor when TCS demand cycles down, but is lower-margin and strategically less important. Q1 2025: CM was 37.7% of revenue, elevated because TCS had a trough quarter.
[Silicon Wafer] → [Fab (TSMC/Intel)] → [Wafer Sort (ATE)] → [Package (OSAT)]
→ [KGD Test] → [Burn-In / SLT Handler ★AEM★] → [ATE Final Test]
→ [System Integration Test] → [OEM (Server/PC/Device)] → [End User]AEM sits at the burn-in handler and SLT system layer — back-end test, between OSAT packaging and final ATE test. This is the most thermally intensive step in the test sequence.
Revenue pool analysis: Back-end test is a ~$6-7B market growing at ~8% CAGR. AEM’s addressable slice is burn-in handlers and SLT — estimated at $1-2B of that total. AEM’s revenue at S$400M is SGD, which at ~0.75 USD/SGD is ~US$300M — approximately 15-30% of the estimated handler/SLT addressable pool, reflecting its Intel concentration.
Key suppliers:
| Supplier | Ticker | Layer | Notes |
|---|---|---|---|
| Precision machined components | Various private | Components | Sourced from Penang/SG ecosystem |
| Electronic sub-assemblies | Various | Sub-systems | CEI (now private after AEM offer) contributed PCBs |
| Thermal interface materials | Various | Materials | Coolant, TIM — commodity |
| Test sockets/contactors | Enplas, LEENO, WinWay | Consumables | Socket replacement is recurring revenue for third parties |
Supplier concentration is low — AEM has no single critical supplier. CEI privatization (S$99.7M in 2021) gave AEM partial vertical integration in PCB assembly, improving supply chain control.
Upstream bottleneck verdict: No single upstream supplier represents a compelling investment-level bottleneck. The value pool resides primarily at AEM (the system integrator with the thermal IP), not in components.
| # | Customer | Ticker | Est. Revenue Share | Relationship Type |
|---|---|---|---|---|
| 1 | Intel | INTC | ~55-60% (FY2025, declining) | 15-yr co-development partner; HDMT/AMPS burn-in + SLT handler |
| 2 | New AI/HPC anchor | Unknown (AMD/NVDA spec.) | Rising to #1 by end-2026 | CPU/GPU burn-in + SLT; growing rapidly |
| 3 | Tier-1 memory customer | Unknown | Near zero today; prod. ramp late FY2026 | Equipment evaluation stage |
| 4 | Intel Foundry customers | Various (via IFS) | Immaterial now, future potential | New channel via May 2025 IFS agreement |
| 5 | Legacy industrial / other | — | ~5-10% | CM + misc. instrumentation |
Intel: the anchor that defines everything - Intel designs its own test methodology and historically does not use standard Teradyne/Advantest testers in the same way — it uses AEM’s custom handlers paired with Intel-proprietary testers (HDMT, HATS). - This co-development architecture means Intel has substantially higher switching costs than a typical equipment customer. Replacing AEM would require re-engineering Intel’s entire back-end test flow, re-qualifying test sockets at new handler, retraining thousands of factory workers, and requalifying chips to automotive/server specs — a 2+ year process. - Intel’s financial health is relevant: Intel is restructuring, cutting capex, and under cost pressure. Demand volatility is structural. However, 18A ramp is Intel’s stated company survival play — they will spend on test equipment. - Intel financial health check: Intel Q1 2026 reported Foundry revenue +20% QoQ; 18A yields running ahead of internal targets. Not in distress; maintaining capital spend on advanced processes.
New AI/HPC anchor customer: - Described by AEM management as a “fabless AI/HPC company” driving massive volume in CPU and GPU testing flows. - Expected to become AEM’s #1 revenue customer by end-2026. - Not confirmed publicly. AMD (NASDAQ: AMD) and NVIDIA (NASDAQ: NVDA) are the primary market speculation targets. Both produce high-power chips (EPYC CPUs, Instinct MI300/MI400 GPUs; H100/B200 GPUs) that require exactly the type of high-power SLT that AEM specializes in. - Switching costs for this customer: once burn-in and SLT infrastructure is qualified and deployed in volume, replacing it is a multi-year process. AEM is in high-volume manufacturing, not evaluation. - Risk: identity unconfirmed; order schedule not publicly disclosed.
Concentration trend: Intel was ~70% in FY2022-23. New customer ramp expected to bring Intel below 50% by end-2026. This is structural diversification — the single most important strategic shift for AEM.
Why it matters: AI chips are getting exponentially more powerful, larger, and more expensive. An NVIDIA B200 GPU retails at $30,000-40,000; a failed chip reaching the customer costs multiples of that in replacement, RMA processing, and reputation damage. The economics of burn-in and SLT are simple: the cost of testing is small compared to the cost of a chip field failure. As chip power and complexity rise, test requirements become more demanding, not less. Chips that passed burn-in in 2018 at 400W now require 2,000W+ test infrastructure in 2025.
End-use applications: - Advanced CPU/GPU burn-in and SLT (Intel, AMD, NVIDIA-class devices) - AI accelerator package testing (Sapphire Rapids, Granite Rapids, EPYC, MI300, B200 class) - High-performance computing (HPC) and AI server chips - Cryogenic wafer probe for quantum computing - Compound semiconductor and power device wafer test
TAM: - Semiconductor test equipment (total): ~USD 15.1B in 2025, projected USD 21.6B by 2031 (CAGR 6.1%; Fortune Business Insights) - Semiconductor test and burn-in solutions specifically: ~USD 6.3B in 2025, projected USD 12.3B by 2033 (CAGR 7.9%; DataInsightsMarket) - Handler and SLT subsegment: no published standalone TAM; estimated at $1-3B based on implied market share analysis - Test cost as % of chip cost rising: was ~5% for mobile SoCs; now 10-15% for advanced AI packages
Market share: AEM dominates burn-in handler supply to Intel’s back-end test operations (40,000+ SLT sites). In the broader handler market, Cohu (NASDAQ: COHU, market cap ~US$900M) is the most direct competitor, but lacks AEM’s high-power thermal capabilities.
Secular tailwinds: 1. AI chip power density rising: B200 at 1,000W, next-gen at 1,500W+ — only AEM-class thermal solutions can test these 2. AI chip complexity: chiplet architectures require SLT because ATE vectors can’t replicate inter-die interactions 3. Intel 18A ramp: technology transition drives new handler investment at Intel’s manufacturing network 4. Advanced packaging growth: EMIB, Foveros, CoWoS — more test insertions per chip 5. Memory test entry: if validated, opens $2-3B+ DRAM test market (DDR5/HBM)
Demand inflection: AI chip volumes are ramping at NVIDIA (B200, B300), AMD (MI300, MI400), and Intel (Gaudi). Each new chip generation is more powerful and more thermally challenging than the prior. This isn’t a cyclical uptick — it’s a structural step-up in the specs required for burn-in and SLT. The addressable market for high-power SLT was effectively zero in 2018; it was created by Intel (with AEM) and is now being adopted by a second customer that represents new-greenfield revenue for AEM.
Supply constraint: AEM’s PiXL thermal technology is patented. There is no off-the-shelf alternative for 2,000W+ burn-in. Cohu competes on standard handlers. Teradyne/Advantest are building SLT capability but lack AEM’s thermal depth and Intel’s 40,000-site installed base. Building a competing thermal handler system requires 5+ years of co-development with a chip customer — the market is not easily entered.
Inventory cycle: FY2023-2024 was deep destocking. Intel pulled forward orders into 2H2024, creating an artificial trough in 1H2025. That trough is now past; 2H2025 revenue of S$209M exceeded guidance. FY2026 guidance of S$460-510M implies restocking to above pre-trough levels.
What has fundamentally changed in the last 12-18 months: 1. AEM secured a second AI/HPC anchor customer who is growing so rapidly they will overtake Intel by end-2026 — the business is no longer a single-customer story 2. Intel 18A yields are ahead of schedule (per Q1 2026 earnings) — deriving the AEM equipment pull-through thesis on Intel 3. Intel Foundry Services agreement (May 2025) creates a new commercial channel: AEM’s ecosystem is available to Intel’s external foundry customers, potentially opening revenue from Qualcomm, Broadcom, and others who may fab on Intel 18A/14A 4. AEM acquired ATECO (South Korea) for memory handler — strategic entry into DRAM/HBM test
What analysts are missing: Consensus is anchored to the Intel relationship. The new customer’s magnitude is not priced into analyst models because its identity is unknown. If it is NVIDIA, the revenue potential at scale would dwarf what Intel ever delivered to AEM, given NVIDIA’s AI chip volumes. The market is pricing a “slightly better Intel story” not a “NVIDIA becoming AEM’s #1 customer” story.
Narrative vs. reality gap: The stock has partly closed this gap (+90% YTD). But at 49x forward P/E on FY2025 earnings, the market is now pricing a significant FY2026-2027 earnings re-rating. If the new customer delivers, estimates will move up. If it slips, the stock could retrace 30-50%.
Near-term (0-12 months): - 1H2026 results (Aug 2026): revenue guidance achievement; new customer ramp visibility - Memory test customer first production delivery (late FY2026) - Intel 18A first external customer win — triggers AEM’s IFS commercial channel - Q1 2026 business update (May 2026): first datapoint on FY2026 ramp
Medium-term (1-3 years): - New AI/HPC customer overtakes Intel by end-2026 — de-concentration milestone - Memory test ramp FY2027: if tier-1 memory customer validates, opens entirely new revenue stream - Intel 14A process: follow-on process after 18A keeps AEM’s Intel revenue durable - Margins: if revenue scales to S$600-800M with fixed cost base, net margins could recover to 10-15%
Why Now (summary): AEM is at the beginning of a multi-year customer diversification that removes its single largest investment risk (Intel concentration). The new customer is ramping in high-volume manufacturing, not evaluation. Intel 18A is delivering ahead of schedule. The company has a clean balance sheet, resumed dividends, and is generating real FCF. The thesis works if: (1) the new customer is real and large (not yet confirmed), (2) Intel 18A ramp continues, and (3) memory test validates on schedule. The risk is that after a 90% move, the margin of safety at 49x forward is thin.
| Name | Title | Tenure | Background |
|---|---|---|---|
| Samer Kabbani | CEO | Jul 2025 – present | 25+ yr semiconductor test; AEM CTO/President 2020-2025; Division President Delta Design (Cohu); EVP Astronics Test Systems (now Advantest); ~40 patents thermal/test automation |
| Chua Tat Ming | COO | Long-tenured | Semiconductor operations background |
| Kwek You Cheer | CFO | Not disclosed | Finance background |
| Loke Wai San | Non-Executive Chairman | Since 2011 | Founder/MD Novo Tellus Capital Partners; 26+ yr technology PE; transformed AEM from sub-S$100M regional to S$870M peak revenue via 7 acquisitions |
CEO change signal: Amy Leong (Jul 2024–Jul 2025) replaced after 12 months following “comprehensive board review.” This is the third CEO in two years (Chandran Nair → Leong → Kabbani). Frequent CEO changes raise yellow flags:
| Name | Role | % Est. | How Acquired | Note |
|---|---|---|---|---|
| Loke Wai San | Chairman | Material (via NT) | PE acquisition 2011 | Founding PE stake; exact current %, not publicly disaggregated |
| James Toh | Director | Material (via NT) | PE acquisition 2011 | Founding PE stake |
| Samer Kabbani | CEO | Small (from employment) | Salary/options/grants | No evidence of open-market purchases |
| Aggregate insiders | — | ~4-5% | Mixed | S$75M aggregate value reported |
Net insider activity (last 12 months): No significant open-market purchases or sales reported in public sources. SGX insider reporting is less granular than US Form 4. Novo Tellus has held since 2011 and has not publicly sold significant blocks — a positive signal of long-term alignment.
Assessment — Skin in the Game: Yellow. Novo Tellus has meaningful long-term skin via its founding stake. But the management team at the executive level (CEO, CFO, COO) appears to have limited open-market ownership. Kabbani’s 40 patents create alignment through intellectual investment, even if not pure financial stake. Not a red flag, but not a strong insider-buying story.
| Name | Role | AWX Holdings | Other Entities |
|---|---|---|---|
| Loke Wai San | Chairman | Via Novo Tellus stake in AWX | Also chairs Grand Venture Technology (GVT.SI); managing partner NT Capital with portfolio across SE Asia tech/industrial |
| James Toh | Director | Via NT stake | Co-founder NT Capital |
| Samer Kabbani | CEO | Employment-derived equity | Former division president Cohu — no overlapping positions identified |
Loke’s cross-holdings flag: Loke Wai San is simultaneously chairman of AEM and involved in Grand Venture Technology (another Singapore listed semiconductor-adjacent company where NT invested S$23.6M in 2021). GVT provides precision engineering services and could theoretically be a supplier to AEM. No formal related-party transaction disclosures involving GVT have been identified in public sources, and AEM’s supply base is reported as primarily from Penang industrial cluster rather than GVT. This warrants monitoring in annual report related-party disclosures, but is not a current red flag.
CEI privatization (2021): AEM offered to privatize CEI Limited (circuit board manufacturer) at S$1.15/share for S$99.7M total. Rationale: vertical integration of PCB assembly, supply chain resilience. CEI was a legitimate arms-length acquisition with a Board-approved fairness opinion. No self-dealing identified.
Registered agent / entity overlap: No shell entities or registered agent overlaps identified via public sources. Novo Tellus is a transparent Singapore-based PE firm with disclosed AUM and fund activities.
Related-party transactions: AEM’s annual reports disclose related-party transactions. No evidence of AEM paying material fees to Novo Tellus or Loke-affiliated entities beyond normal director remuneration.
Verdict: Green. No shell entity patterns, no asset migration red flags, no revenue circularity identified. Governance appears clean for a Singapore-listed company with PE founding sponsorship.
Acquisitions: - CEI Limited (2021): S$99.7M to privatize circuit board maker. Rationale (vertical integration) was sound; supply chain control improved. Timing was at peak AEM revenues — the acquisition has been absorbed but no clear value creation vs. destruction reported publicly. - ATECO Inc (South Korea): ~US$3.8M for memory handler design capability. Small, strategic. Enabled memory test market entry. - Afore (Finland): acquisition (pre-2020) that created the Instrumentation/wafer test segment. Enabled quantum computing prober capability and Finland R&D. Size not disclosed publicly. - Grand Venture Technology: This was a Novo Tellus investment (23.45% stake), not an AEM acquisition.
Buybacks: No significant share repurchase programs identified. Share count essentially flat at ~311-315M from FY2021-FY2025. No dilution = positive; no buybacks at trough prices (FY2023-24) = missed opportunity.
Dividends: Paid dividends in FY2021 (S$18.6M), FY2022 (S$36.2M), FY2023 (S$11.1M). Suspended in FY2024; resumed in FY2025 at S$0.013/share (one-time payment of ~S$4M). Dividend history is volatile — reflects opportunistic payout rather than consistent capital return policy.
Capex efficiency: Capex has been S$4-13M per year on revenues of S$380-870M — capex intensity of 1-2%. Very efficient; the business is asset-light relative to its revenue base. Incremental revenue per capex dollar has been extremely high historically.
Capital allocation grade: B. Asset-light model is strong. Dividend volatility is a mild negative. CEI acquisition was defensible. Missed buyback opportunity at FY2023-24 trough prices is suboptimal but understandable given the balance sheet was in net debt. ATECO was a sensible small strategic add. No major value-destroying M&A.
AEM is Singapore-listed; executive compensation disclosed annually in the Annual Report. Details on specific CEO comp not captured in available public summaries. For SGX companies, compensation disclosure is typically by band (S$250K increments for directors, more detail for top executives). SBC levels are not flagged as excessive in public analyst commentary. No related-party perks identified.
| Name | Role | Independent? | Background | Committee |
|---|---|---|---|---|
| Loke Wai San | Non-Exec Chair | No | Co-founder/MD Novo Tellus; AEM chairman since 2011 | Nominating |
| Alice Lin | Independent Director | Yes | Former CFO Oracle Asia Pacific; Green Mountains Investments | Audit & Risk (Chair) |
| Russell Tham | Non-Exec, Non-Independent | No | Head Strategic Development Temasek International; represents 12.46% Temasek stake | — |
| Loh Kin Wah | Independent Director | Yes | 30+ yr semicon; ex-CEO Qimonda; ex-EVP NXP; AMS AG Supervisory Board | Audit & Risk, Technology |
| James Toh | Non-Exec, Non-Independent | No | Founding director Novo Tellus | — |
| André Andonian | Independent Director | Yes | 34 yr McKinsey; ex-Managing Partner McKinsey Japan/Korea; semiconductor consulting | Nominating (Chair) |
| Chok Yean Hung | Non-Exec, Non-Independent | No | Former CEO, 30+ yr semiconductor; known for building start-up to listed companies | — |
Board quality observations: - 3 of 7 directors are independent — below typical 50%+ threshold for strong governance. However, Temasek’s presence (12.46% stake, board seat) provides institutional oversight. - Loh Kin Wah (ex-Qimonda, NXP, AMS) brings genuine semiconductor operational depth. Alice Lin (Oracle CFO) brings financial rigor. Andonian (McKinsey, semiconductor consulting) brings strategic perspective. - Non-independent directors are all aligned with long-term holders (Novo Tellus, Temasek) — not random friends of management. - No dual-class shares; no poison pill identified; no staggered board identified. - Governance red flags: none significant. The Novo Tellus over-representation on the board (Chair + 1 director) warrants monitoring, but NT’s interest is aligned with long-term value creation given their 2011 entry price.
| Dimension | Rating | Key Finding |
|---|---|---|
| Skin in the Game | Yellow | Novo Tellus long-term alignment; executive team has limited open-market purchases |
| Holdings Concentration | Green | No conflicting cross-holdings identified; GVT overlap minor |
| Shell / Cross-Holdings | Green | No shell entities, no asset migration patterns |
| Capital Allocation | B (Yellow-Green) | Asset-light, sensible tuck-ins, missed buyback opportunity at trough |
| Compensation Alignment | Yellow | SGX disclosure limited; no excessive SBC flagged |
| Governance Quality | Yellow-Green | 3/7 independent; strong anchor holders offset board independence gap |
| Litigation / Enforcement | Green | No material litigation or regulatory enforcement identified |
| Overall Management Grade | B / Yellow-Green | Technically strong leadership, reasonable governance, PE founding with long-term skin |
| Company | Ticker | Focus | Revenue (~2025) | Moat Type |
|---|---|---|---|---|
| Teradyne | TER (NASDAQ) | ATE, SLT, robotics | ~US$3.0B | ATE IP, robotics scale, customer relationships |
| Advantest | 6857 (TSE) | ATE (SoC + memory), SLT building | ~US$4.0B | ~58% SoC ATE market share, AI chip qualification |
| Cohu | COHU (NASDAQ) | Handlers, contactors, test sockets | ~US$0.5B | Handler installed base, Xcerra integration |
| Aehr Test Systems | AEHR (NASDAQ) | Wafer-level burn-in (SiC/GaN) | ~US$0.1B | WLP burn-in IP for power semis |
| AEM Holdings | AWX (SGX) | Burn-in/SLT handlers for advanced logic | ~US$0.3B | PiXL thermal IP, Intel 40,000-site installed base |
AEM’s moat vs. peers: - vs. Teradyne/Advantest: AEM doesn’t compete in ATE — they are complementary. AEM’s AMPS connects to Intel’s own testers. However, both Teradyne and Advantest are building SLT capability; if they develop high-power thermal solutions, they could encroach on AEM’s niche. - vs. Cohu: Most direct competition in handlers. Cohu’s thermal capability maxes out at ~400-500W per device. AEM’s PiXL at >2,000W is in a different tier. Cohu cannot serve the AI chip burn-in requirement without a major technology development effort. - vs. Aehr: Different market — Aehr focuses on wafer-level burn-in for SiC and GaN power devices (EV, solar). Not an overlap with AEM’s back-end SLT for logic/AI.
5-year lock-up test: Yes, I’d own this for 5 years, but with eyes open. The business solves a real problem with proprietary technology. Intel concentration remains the anxiety. If the new AI/HPC customer ramp delivers and is durable, this becomes a significantly more attractive business than what the last three years showed.
Unique economic engine: AEM’s economic engine is: (1) high technical barrier to entry via PiXL thermal IP and Intel co-development history; (2) sticky installed base (40,000 SLT sites requiring replacement of sockets, boards, and eventually new systems); (3) expanding TAM as AI chips push thermal requirements higher. The source of uniqueness is the 15-year co-development relationship with Intel that produced an installed ecosystem competitors cannot replicate without their own 10+ year partnership at a comparable chip maker.
Blank-check disruptor: A well-funded competitor (Teradyne/Advantest) could theoretically build competing thermal handlers — they have the R&D scale. The protection is Intel’s qualification lock-in (replacing AEM would require multi-year requalification), the 40,000-site installed base (service revenue and upgrade revenue), and AEM’s IP. A blank-check entrant would need 5+ years to qualify, not just build. For the new AI/HPC customer, AEM is already in production — the moat is being rebuilt at the second anchor.
Quality verdict: Durable, with caveats. The thermal moat is real and growing. Customer concentration at Intel is the structural vulnerability. The two-customer story that is emerging (Intel + new AI/HPC) significantly improves quality. Not a compound compounder, but not a commodity handler maker either.
Structure: Handler/SLT market is moderately fragmented. AEM is the dominant pure-play burn-in/SLT handler for high-power logic chips; Cohu leads in standard handlers; Tokyo Seimitsu and TEL lead in wafer probers; Advantest/Teradyne dominate ATE. No single company spans all layers.
Barriers to entry: Customer qualification cycles (12-24 months minimum for a new handler to qualify at a chip maker), co-development relationships (Intel-AEM is a 15+ year partnership), and IP (PiXL patents). High for AEM’s specific niche.
Cyclicality: Highly cyclical — as demonstrated by FY2022 peak (S$870M) to FY2024 trough (S$380M). The cycle is driven by chip maker capex, which is in turn driven by semiconductor demand cycles. AI/HPC is a secular growth driver overlaid on the cycle, but Intel’s specific inventory management created an artificial 2-year air pocket that AEM is now recovering from.
Cycle position: As of Q1 2026, AEM is at early-to-mid recovery phase. Revenue growing, but still well below FY2022 peak. New customer ramp is additive, not a cyclical recovery per se — it represents genuinely new revenue. Intel 18A ramp is the cyclical recovery component.
Leading indicators: - Intel quarterly capex commentary and back-end test investment guidance - Intel 18A external customer wins (TSMC’s equivalent of “risk production” starts) - AEM quarterly revenue and order book disclosures (SGX reports semi-annually + quarterly updates) - Global SLT site count announcements from AEM (proxy for market penetration)
Teradyne/Advantest SLT encroachment: Both are building SLT capability. Advantest’s 7038 SLT system is expanding. If they add thermal management depth, they threaten AEM’s niche with greater scale and customer trust from the ATE side of the relationship.
Intel internalization risk: Intel could theoretically develop its own handler solutions rather than sourcing from AEM. This risk is low given the co-development history and the fact that AEM serves multiple new customers Intel doesn’t control.
Chinese competition: Chinese test equipment makers (Cohu’s Chinese competitors, domestic brands) are expanding, primarily for domestic chip makers. Limited near-term threat to AEM’s high-power niche, but a long-term risk as Chinese chip technology advances.
New packaging technology: If chiplet architectures shift test to wafer-level KGD testing (where AEHR, AEM’s Finland division, Tokyo Seimitsu compete), AEM’s back-end SLT market could be disrupted. This is a 5+ year horizon risk.
AMD or NVIDIA insourcing: If either speculated new customer decided to build their own test handler capability, AEM loses the diversification thesis. Low probability — chip makers do not typically build their own test equipment when a qualified supplier exists.
1. Organic revenue growth: AEM’s organic revenue growth has been violently cyclical. FY2022 peak at S$870M (+54% YoY) driven by Intel pull-forward during HDMT ramp; FY2023 (-45%) and FY2024 (-21%) driven by Intel inventory correction; FY2025 (+5%) the first recovery year. Intel-only analysis: AEM is essentially a single-customer cyclical equipment maker in its legacy profile. The new customer changes this.
2. Margins: Gross margins at FY2022 peak: 31.4%. At FY2024-25 trough: 25.7%. The 6 percentage point compression reflects: (1) lower revenue over fixed cost base, (2) higher CM mix (lower margin), (3) potentially unfavorable pricing on Intel at lower volumes. Returning to 30%+ gross margin requires revenue scale and favorable mix shift (TCS > CM). At S$500M revenue, assuming similar GM% recovery, operating leverage could drive EBIT margins from 6.5% (FY2025) toward 12-15%.
3. Capital intensity: Capex S$4-13M/year on S$380-870M revenue = 1-2% capex intensity. This is genuinely asset-light. Working capital is the constraint — inventory builds during ramp-ups create negative OCF years (FY2022: OCF -S$31M from inventory build; FY2024: OCF -S$18M). FY2025 massive FCF of S$128M reflects inventory liquidation, not operating earnings — the “real” operating FCF at trough earnings is closer to S$25-30M.
4. Capital deployment: Flat share count over 5 years (no dilution). CEI acquisition at S$99.7M was defensible. ATECO at US$3.8M was smart. No buybacks. Dividend resumed. Net cash S$61M entering FY2026 — balance sheet can fund organic growth without dilution.
AEM reports semi-annually (not quarterly ATE). Available half-year data:
| Period | Revenue (S$M) | YoY Change | Commentary |
|---|---|---|---|
| 1H2023 | ~241 | — | — |
| 2H2023 | ~240 | — | — |
| 1H2024 | ~173 | -28% (est.) | Intel inventory trough |
| 2H2024 | ~207 | -14% (est.) | Intel pull-forward into 4Q |
| 1H2025 | ~190 | +10% | Recovery; guided S$155-170M, beat |
| 2H2025 | ~209 | +1% | Above guidance S$170-190M; beat |
| Q4 2025 | ~112 | -16% | YoY dec. vs. strong Q4 2024 |
Second derivative assessment: Revenue trajectory is recovering (1H2025 +10% YoY), but Q4 2025 showed a YoY decline (-16%) because 2H2024 was artificially elevated by Intel pull-forward. The underlying trend is positive — 1H2025 beat guidance, 2H2025 beat guidance. FY2026 guidance of S$460-510M (+15-28% YoY) represents meaningful acceleration if achieved.
Key question: Is FY2026 guidance conservative or aggressive? Management guided 1H2025 at S$155-170M and delivered S$190M. 2H guidance of S$170-190M delivered S$209M. Both beats were material. FY2026 midpoint of S$485M implies +21% YoY — achievable if new customer ramp executes as described.
| Metric | Value (Apr 26, 2026) |
|---|---|
| Market cap | S$1.91B |
| EV | ~S$1.85B |
| P/E (TTM) | 113x |
| Forward P/E (FY2026E) | 49x |
| EV/EBITDA | 44x |
| P/FCF | 14.9x (FY2025 FCF) |
| EV/Revenue | 4.6x |
| FCF yield | 6.7% (FY2025 FCF — trough earnings, inventory liquidation) |
| Dividend yield | 0.2% |
| 52-week range | S$1.15 – S$6.15 |
Valuation context: - At S$6.06, the stock is pricing in a substantial recovery. At 49x forward P/E, the market is paying for ~FY2026E earnings of ~S$39M (implied from S$1.91B / 49x = S$39M). That requires meaningful margin expansion from FY2025’s S$17M — achievable at S$480-510M revenue, not certain. - EV/FCF of 14.9x looks cheap, but FY2025’s S$128M FCF is inflated by S$65-70M inventory liquidation. Normalized FCF at S$400M revenue and 6% FCF margin = ~S$25M, or EV/FCF of ~74x. Less compelling. - Comparable ATE names: Teradyne trades at ~20-25x forward EBIT; Advantest at 35-40x forward P/E. AEM at 49x forward P/E is at a premium to ATE despite being a handler integrator with lower structural margins — reflects the new-customer optionality premium. - Where valuation could go: If new customer delivers and FY2026 revenue hits S$500M with gross margins recovering to 27-28% and net margins at 7-8%, EPS could be S$0.10-0.12/share. At 30x P/E = S$3.00-3.60. At 40x = S$4.00-4.80. At current S$6.06, the market is pricing 50x+ on optimistic FY2026 EPS — or pricing material FY2027 earnings power.
| Metric | FY2022 | FY2023 | FY2024 | FY2025 (LTM) | FY2026E |
|---|---|---|---|---|---|
| Revenue | 870.5 | 481.3 | 380.4 | 399.3 | 460–510 |
| Growth YoY | +53.9% | -44.7% | -21.0% | +5.0% | +15–28% |
| Gross profit | 273.7 | 129.3 | 97.6 | 102.5 | N/A |
| Gross margin | 31.4% | 26.9% | 25.7% | 25.7% | ~26-28% est. |
| EBIT | 160.7 | 43.9 | 16.0 | 26.0 | N/A |
| EBIT margin | 18.5% | 9.1% | 4.2% | 6.5% | N/A |
| Net income | 126.8 | (1.2) | 11.4 | 17.0 | N/A |
| Net margin | 14.6% | neg | 3.0% | 4.3% | ~7-10% target |
| EPS (S$) | 0.41 | (0.00) | 0.04 | 0.05 | N/A |
| Metric | FY2022 | FY2023 | FY2024 | FY2025 |
|---|---|---|---|---|
| Operating CF | (31.4) | 40.2 | (17.5) | 136.0 |
| Capex | (12.8) | (7.7) | (5.9) | (7.7) |
| FCF | (44.2) | 32.4 | (23.4) | 128.2 |
| FCF margin | neg | 6.7% | neg | 32.1% |
| Net cash/(debt) | (11.5) | (20.2) | (50.6) | 61.0 |
| Net debt / EBITDA | 0.1x | 0.5x | 1.2x | net cash |
| ROIC | 33.5% | (1.4%) | 2.6% | 4.3% |
ROIC vs. WACC: - ROIC at FY2025: 4.3% (trough earnings; WACC ~3.67% per Gurufocus 2024) - ROIC vs WACC: marginally above at trough. At FY2022 peak, ROIC was 33.5% vs WACC ~4% — the business creates extraordinary value at scale. The cycle destroyed value creation temporarily. - Implication: AEM is a value creator at scale (33.5% ROIC vs. ~4% WACC = massive spread), but only at the revenue levels achieved in FY2021-22. At current trough, ROIC barely covers WACC. The bull thesis is that revenue recovery to S$500-800M restores ROIC to 15-30% range.
Limited by semi-annual reporting. Using available 1H/2H data to proxy quarterly incrementals:
| Period | Delta Revenue (YoY, SM)|DeltaGrossProfit(YoY, SM) | Inc. GM | Delta EBIT (YoY) | Inc. EBIT | |
|---|---|---|---|---|---|
| 1H2025 vs 1H2024 | +~17 (est.) | +~4 (est.) | ~24% | +~5 | ~29% |
| 2H2025 vs 2H2024 | +~2 | ~flat | — | — | — |
| FY2025 vs FY2024 | +18.9 | +4.9 | 26% | +10.0 | 53% |
FY2025 incremental analysis: - Revenue: +S$18.9M (4.98% growth) - Gross profit: +S$4.9M → incremental GM 26% (in line with base, no leverage) - EBIT: +S$10.0M → incremental EBIT margin 53% — significant operating leverage on small revenue increment - This suggests meaningful fixed-cost leverage is emerging even at modest revenue growth
What the incrementals tell us: AEM appears close to an operating leverage inflection. At FY2025’s revenue base of S$399M, each additional dollar of revenue drops ~50% to EBIT. If FY2026 adds S$80-110M of revenue as guided, EBIT could improve by S$40-55M, bringing EBIT from S$26M to S$65-80M — and net income from S$17M to S$45-55M. That would make the current 49x forward P/E look more reasonable.
This leveraged operating model is the core upside scenario. The risk is if new customer margins are lower than Intel’s (possible if the new customer negotiated hard on pricing given their scale).
Base case (FY2026E — guidance midpoint S$485M revenue): - Gross margin: 26.5% → gross profit S$128M - EBIT margin: 9% → EBIT S$44M (applying recent incremental leverage to guidance) - Net income (est.): ~S$35-40M - EPS: ~S$0.11-0.13 - At S$6.06 / S$0.12 EPS = 50x P/E → expensive for a handler OEM
Bull case (FY2027E — S$600M revenue, memory test ramp starts): - Gross margin: 28% → gross profit S$168M - EBIT margin: 12% → EBIT S$72M - Net income: ~S$55-60M - EPS: ~S$0.17-0.19 - At 35x P/E on FY2027 EPS: S$6.00-6.60 — roughly where the stock trades today
Conclusion on valuation: The stock at S$6.06 is pricing the bull case on FY2027 EPS — which is 2 years of execution at the new customer ramp rate. There is little margin of safety. If the thesis executes exactly as management suggests, the stock is fairly valued at current levels. If execution slips 6-12 months, there is 30-40% downside to the S$3.50-4.50 range where the FY2026 earnings scenario reprices the stock.
| Risk | Likelihood | Existing Mitigants | Mgmt De-risk Plan | Can It Be Closed? |
|---|---|---|---|---|
| Intel concentration | High — Intel still ~55-60% of FY2025 revenue | 40,000-site installed base = high switching cost; 18A ramp maintains demand | New customer overtaking Intel by end-2026; memory test entry | Partially — Intel contribution declining; not closable to zero given relationship depth |
| Intel 18A execution failure | Medium — yields ahead of schedule as of Q1 2026, but Intel has history of delays | Intel committed 18A as company survival; yields improving; AEM diversifying to non-Intel | Customer diversification reduces dependence | Not fully closable — any Intel stumble reduces AEM demand; mitigated by diversification |
| New customer identity/ramp slip | Medium — customer unidentified; schedules can slip | Customer in HVM already (not evaluation); 2H2025 revenue beat shows ramp integrity | CEO Kabbani’s technical credibility with customers; order visibility via internal pipeline | Partially closable — closes on confirmed production milestones; binary until visible |
| Margin compression | Medium-High — gross margin 25.7% vs. 31.4% peak; new customer pricing unknown | Variable cost structure limits downside; clean balance sheet | Revenue scale to S$500M+ targets 10% net margin; no formal gross margin guidance | Structural — depends on new customer pricing; closable if revenue mix normalizes |
| CEO transition instability | Medium — third CEO in two years; Leong replaced after 12 months | Kabbani is internal, knows product and customers; board acted decisively | No stated succession plan | Manageable — Kabbani’s technical depth is strong; monitor over next 12 months |
| Advantest/Teradyne SLT encroachment | Low-Medium — both building SLT; thermal gap is large | PiXL IP patented; 40,000 Intel sites = massive switching cost | Continuous thermal spec improvement; extend into memory test | Not fully closable — Teradyne/Advantest scale is 10x AEM; if they prioritize this space, threat grows |
| AI demand shock | Low-Medium — if hyperscaler capex cuts, chip volumes decline | Intel is CPU not pure AI; non-Intel customer diversification | Geographic diversification; multiple customers | Partially closable via diversification; macro risk cannot be eliminated |
What would make the thesis wrong: 1. New AI/HPC customer (if AMD) delays CPU volume ramp due to competitive dynamics with Intel 18A; AEM loses the key revenue driver for FY2026 2. Intel 18A yields plateau before external customer wins; IFS remains sub-scale; Intel’s own AI equipment investment is limited by budget constraints 3. Teradyne/Advantest build competing high-power SLT solution in 18-24 months using their greater R&D resources
Bear case financials: Revenue stays at S$380-420M, margins remain at 25-26%, EPS barely above S$0.05. At 25x P/E = S$1.25 stock price. ~80% downside from current S$6.06.
Bear case probability: Low-Medium (20-30%). The new customer is already in HVM, so the complete absence of ramp is unlikely. More realistic bear: ramp slips 12-18 months, revenue hits S$420-440M in FY2026 vs. guided S$485M, stock reprices to S$3.00-4.00 (50-35% downside).
Thesis invalidation criteria: - FY2026 revenue guidance cut below S$420M with no new customer named - Intel 18A yielded results significantly miss internal targets (per subsequent Intel earnings) - Management confirms new customer is smaller than Intel’s historical contribution
| Holder | Type | Who They Are | % Outstanding | Source |
|---|---|---|---|---|
| Temasek Holdings (Tembusu, Napier, Venezio subs) | Government-linked | Singapore sovereign wealth / strategic state investor; Russell Tham (Head Strategic Dev) on board | 12.46% | SGX substantial shareholder disclosure, Dec 2024 |
| EPF Malaysia | Government pension | Malaysian national pension fund; long-term institutional anchor; passive-style holding | 9.51% | SGX substantial shareholder disclosure, Dec 2024 |
| abrdn plc | Active institutional | Edinburgh-based global active manager (~US$500B AUM); tech/Asia exposure; would be thesis-driven hold | 5.93% | SGX substantial shareholder disclosure, Dec 2024 |
| Novo Tellus Capital Partners (Loke / Toh) | PE / founding | Founding PE firm; 2011 acquisition; Loke is chairman; long-term holder via unlisted PE fund structures | Material (est. 5-10%+) | Board representation; SGX insider disclosures |
| Public / retail / other institutional | — | Singapore retail investor community active in AWX; SGX-listed stocks have significant retail ownership | ~60%+ | Implied residual |
Conviction level: Medium. - Thesis is real and well-supported. - Stock has already moved +90% YTD; entry at S$6.06 is not a margin-of-safety entry. - The business is at an inflection but valuation reflects most of the near-term upside.
Entry strategy: - At current price: not a screaming buy; wait for a pullback to S$4.00-5.00 range (25-35% below current) for better risk/reward - Alternatively, a small pilot position now (0.5-1% of portfolio) to stay engaged, with planned scaling on: (1) Q1 2026 business update confirms new customer ramp trajectory, or (2) stock pulls back to S$4.50-5.00 range on any sector weakness
Position sizing at S$5.00 (target entry): - At S$5.00, forward P/E on FY2026 guidance midpoint falls to ~40x — still expensive but more reasonable - Suggested size at S$5.00: 1.5-2.5% of portfolio (medium conviction, non-trivial risk) - At S$4.00: 2.5-3.5% of portfolio
Stop-loss / re-evaluation triggers: - FY2026 revenue guidance cut (below S$430M) → re-evaluate; reduce - New customer identity confirmed and is smaller than AMD/NVIDIA in chip volumes → re-evaluate - CEO transition leads to further leadership instability → reduce
What would cause adding: - New customer identity confirmed as NVIDIA or AMD (volume potential is enormous) - FY2026 1H results significantly above guidance (AEM has a track record of beating) - Memory test production validation announced on schedule